Multiplication forms the foundation of many digital computations and is widely used in processors, DSP architectures, image-processing units, and embedded systems. The efficiency of a hardware multiplier greatly affects the speed and power consumption of the entire system. This work presents the design and implementation of an optimized 16-bit Wallace Tree Multiplier that incorporates exact 5:2 compressors along with a 32-bit Han-Carlson Parallel Prefix Adder for the final addition phase. The use of 5:2 compressors significantly decreases the number of intermediate reduction levels, helping to shorten the critical path and improve computational throughput. To further enhance hardware efficiency, MUX-based Half and Full Adders are integrated within the reduction layers to lower switching activity and area utilization. The proposed architecture is described in Verilog HDL, synthesized and analyzed using Xilinx Vivado, and deployed on a Basys-3 FPGA board to validate its real-time functionality. Experimental results reveal that the developed multiplier achieves superior performance compared to traditional designs that rely on 4:2 compressors or larger prefix adders. Considerable improvements were observed in delay, power consumption, and LUT utilization. These results highlight the suitability of the architecture for high-speed and power-constrained digital applications. Overall, the study demonstrates that carefully combining compressor-based reduction stages with an efficient prefix adder can offer a well-balanced and high-performance hardware multiplier design.

This work presents an enhanced 16-bit Wallace Tree Multiplier that incorporates exact 5:2 compressors, MUX-based adders, and a Han-Carlson parallel prefix adder to achieve a more efficient multiplication architecture. By restructuring the partial product reduction process and employing a faster final addition stage, the proposed design delivers improvements in speed, energy efficiency and silicon resource usage when compared with conventional approaches. Incorporating MUX-oriented arithmetic components helps reduce switching activity and logic complexity, contributing further to the overall gains. The complete multiplier was described in Verilog, synthesized through the Xilinx Vivado environment, and implemented on the Basys-3 FPGA board, where hardware testing verified its correct functionality. The evaluated parameters show that the design offers a dependable and well-optimized solution for high-speed arithmetic processing. With lower delay and better resource utilization, the proposed multiplier is highly suitable for advanced VLSI applications, including embedded systems, DSP operations, and real-time computational platforms.

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