The demand for high-speed, low-power, and area-efficient hardware architectures has become essential in modern digital signal processing (DSP) systems and contemporary communication technologies. Finite Impulse Response (FIR) filters play a crucial role in these applications by ensuring stable and accurate signal manipulation, but their conventional designs often suffer from large hardware complexity, high propagation delay, and excessive power consumption. To address the drawbacks observed in earlier designs, this work proposes a high-performance 3-parallel polyphase FIR filter structure tailored specifically for odd-length filters. that integrates a Knowles adder and a compressor-based Dadda multiplier for optimized performance in Very Large Scale Integration (VLSI) applications. The design leverages a parallel polyphase structure to enhance throughput and computational speed, while the Dadda multiplier with compressor logic reduces the total count of intermediate partial-product compression levels, minimizing delay and switching power. The Knowles adder, with its balanced prefix tree structure, further improves speed and reduces interconnection complexity compared to conventional adders. The architecture introduced in this work is modeled in Verilog HDL, simulated and synthesized using Xilinx Vivado, and implemented on the Basys 3 FPGA board to validate its performance. Experimental results demonstrate that the developed FIR filter design achieves significant improvements in speed, area utilization, and power efficiency when evaluated against conventional FIR implementations that rely solely on basic multiplier–adder arrangements. The obtained outputs confirm accurate filtering operation, while synthesis results show reduced logic utilization and achieves a noticeably shorter critical path. Because of its improved computational performance, making the architecture highly appropriate for real-time DSP, biomedical processing, wireless communication, and other embedded VLSI applications.

The proposed Efficient 3-Parallel Polyphase Odd-Length FIR Filter utilizing a Knowles Adder and Compressor-Based Dadda Multiplier has been effectively designed and implemented to achieve enhanced performance in terms of speed, power, and area. Through simulation and FPGA realization on the Basys 3 board, the system demonstrated accurate functional behavior and stable hardware operation. The optimized combination of the Dadda multiplier and 4:2 compressor greatly minimized the number of intermediate partial-product compression levels, minimizing propagation delay. Meanwhile, the Knowles adder provided faster carry computation with reduced wiring complexity, contributing to a more area-efficient and high-speed filter architecture. The experimental analysis revealed notable improvements over existing FIR filter designs. The proposed architecture demonstrates notable improvements across all performance metrics. It requires only 41 LUTs, leading to a smaller hardware footprint and using a low power of 0.093 W and achieving a minimized delay of 7.46 ns. These results show superior efficiency compared with conventional FIR filters and those based on Brent–Kung and Booth multipliers. Such enhancements make the design highly suitable for real-time DSP applications where rapid computation and low-energy operation are essential. The architecture may be further extended in the future to support higher-order filters, adaptive systems, or reconfigurable FPGA-based DSP platforms, offering broader scalability and enhanced functionality.

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