The application requires balance between accuracy and speed with high-performance approximate adders is presented in this work. Least significant part and most significant part is combined by this adder with exact computation which uses carry speculative technique. The delay and carry chain length is reduced by this proposed method. To improve accuracy the error detection and recovery mechanism. To four different parallel prefix adder architecture carry speculation is applied to determine the proposed system effectiveness. Based on the area, power, and delay the proposed approximate carry speculative parallel prefix adders (AxPPAs) are implemented in comparison with the existing approximate adders. The proposed system decreases the power, area and delay. The ModelSim is used as a simulation tool and Xilinx is used to find the effectiveness of proposed system with delay, area and power calculation.

A new approximate hybrid adder is proposed and compared with various parallel prefix adders.The POs of the prefix computation phase are calculated using the established approximation technique. The AxPPA proposals are made for certain case studies and are not dependant on any particular application.Block based carry speculative logic is applied to MSP to minimize area and power consumption. Considering various metrices the proposed method provides the higher efficiency. In contrast to the usual method the the capability consumption and energy consumption is more in the proposed hybrid architecture. The proposed adder results in 17.4% resource optimization and 3.5% power reduction compared with Kogge stone adder, which is in an average better of other types of approximate parallel prefix adders.

[1]P. Pereira et al., “Energy-quality scalable design space exploration of approximate FFT hardware architectures,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 69, no. 11, pp. 4524–4534, Nov. 2022. [2]M. M. A. da Rosa, G. Paim, R. I. S. J. Castro-Godínez, E. A. C. Costa, and S. and Bampi, “AxRSU: Approximate radix-4 squarer uni,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), Austin, TX, USA, Jun. 2022, pp. 1–4. [3]G. Paim, H. Amrouch, E. A. C. D. Costa, S. Bampi, and J. Henkel, “Bridging the gap between voltage over-scaling and joint hardware accelerator-algorithm closed-loop,” IEEE Trans. Circuits Syst. Video Technol., vol. 32, no. 1, pp. 398–410, Jan. 2022. [4]R. Roy et al., “PrefixRL: Optimization of parallel prefix circuits using deep reinforcement learning,” in Proc. 58th ACM/IEEE Design Automat. Conf. (DAC), Dec. 2021, pp. 853–858. [5]K.-L. Tsai, Y.-J. Chang, C.-H. Wang, and C.-T. Chiang, “Accuracyconfigurable Radix-4 adder with a dynamic output modification scheme,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 68, no. 8, pp. 3328–3336, Aug. 2021. [6]J. Lee, H. Seo, H. Seok, and Y. Kim, “A novel approximate adder design using error reduced carry prediction and constant truncation,” IEEE Access, vol. 9, pp. 119939–119953, 2021. [7]K. M. Reddy, M. H. Vasantha, Y. B. N. Kumar, and D. Dwivedi, “Design of approximate booth squarer for error-tolerant computing,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 28, no. 5, pp. 1230–1241, May 2020. [8]Z. G. Tasoulas, G. Zervakis, I. Anagnostopoulos, H. Amrouch, and J. Henkel, “Weight-oriented approximation for energyefficient neural network inference accelerators,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 67, no. 12, pp. 4670–4683, Dec. 2020. [9]M. Pashaeifar, M. Kamal, A. Kusha, and M. Pedram, “A theoretical framework for quality estimation and optimization of DSP applications using low-power approximate adders,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 66, no. 1, pp. 327–340, Jan. 2019. [10]Omid Akibari et al. “Improved Efficiency of Reconfigurable Approximate Look-Ahead Adder” IEEE Transactions on Circuits and Systems II: Express Briefs PP(99):1-1 DOI:10.1109/TCSII.2016.2633307. Nov. 2016. [11] N. Zhu, W. L. Goh, W. Zhang, K. S. Yeo, and Z. H. Kong, “Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 8, pp. 1225–1229, Aug. 2010. [12]R. P. Brent and H. T. Kung, “A regular layout for parallel adders,” IEEE Trans. Comput., vol. C-31, no. 3, pp. 260–264, Mar. 1982. [13]R. Ladner and M. Fischer, “Parallel prefix computation,” J. ACM, vol. 27, pp. 831–838, Oct. 1980. [14] P. M. Kogge and H. S. Stone, “A parallel algorithm for the efficient solution of a general class of recurrence equations,” IEEE Trans. Comput., vol. C-22, no. 8, pp. 786–793, Aug. 1973. J. Sklansky, “Conditional-sum addition logic,” IEEE Trans. Electron. Comput., vol. EC-9, no. 2, pp. 226–231, Jun. 1960.

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