Durgashree M N, Hemanth Kumar A R, Chandra Mohan Umapathy

DOI: https://doi.org/10.5281/zenodo.20838770

The growing demand for energy-efficient embedded and digital signal processing (DSP) systems has increased the need for low-power processor architectures. In synchronous digital systems, unnecessary switching activity and continuous clock propagation contribute significantly to dynamic power consumption. Clock gating has emerged as an effective low-power design technique for reducing redundant switching activity without affecting functional operation. This work presents the integration of a DSP-oriented Multiply-Accumulate (MAC) unit along with clock-gating optimization in the SHAKTI C-Class processor, an open-source RISC-V based architecture. The proposed MAC architecture incorporates operand isolation and enable-controlled operation to support arithmetic-intensive DSP computations while minimizing unnecessary transitions. The design was implemented using Verilog HDL and synthesized using the SCL180 standard-cell library. Synthesis results demonstrate a reduction of 14.5% in leakage power, 15.6% in internal power, 26.5% in switching power, and 16.7% in overall total power consumption compared to the baseline architecture. The optimized design incurs only a 2.8% area overhead and a negligible 0.3% timing degradation, demonstrating an effective trade-off between power efficiency and hardware resources. The results validate the effectiveness of combining clock gating and DSP-oriented MAC integration for developing energy-efficient embedded processor architectures.

SHAKTI C-Class Processor, RISC-V Architecture, Clock Gating, Low-Power Design, Multiply-Accumulate (MAC) Unit, DSP Accelerator, Dynamic Power Reduction

The final optimized architecture incorporating both MAC integration and clock-gating techniques was synthesized and evaluated against the baseline SHAKTI C-Class processor. Leakage power was reduced by 14.5%, internal power by 15.6%, and switching power by 26.5%. Consequently, the overall total power consumption was reduced by 16%, demonstrating the effectiveness of the proposed low-power optimization approach.

The reduction in switching power can be attributed to the clock-gating mechanism, while the reduction in internal power results from lower switching activity within the sequential and combinational logic. The optimized design incurred a modest increase of 2.8% in area and 5.5% in net count due to the additional MAC hardware and clock-gating circuitry. Timing analysis indicated a degradation of only 0.3%, which is negligible compared to the substantial reduction in power consumption.

Future work should explore further optimization of the MAC unit architecture, integration of additional DSP accelerators, and evaluation across different standard-cell libraries and technology nodes to further enhance power efficiency for embedded and IoT applications.

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Durgashree M N, Hemanth Kumar A R, Chandra Mohan Umapathy (2026). Power-Efficient Shakti C-Class Processor for DSP Accelerator. International Journal of Engineering and Techniques, 12(3), 636–639. ISSN: 2395-1303. DOI: https://doi.org/10.5281/zenodo.20838770