This work presents the design and implementation of a single precision floating‑point unit (FPU) on a Field‑Programmable Gate Array (FPGA). FPGAs offer key strengths like hardware reconfigurability, parallel processing, and low‑latency execution, making them ideal for custom arithmetic acceleration. Floating‑point representation brings major benefits such as wide dynamic range and high numerical precision, allowing both very large and very small values to be handled efficiently. The FPU performs arithmetic operations including addition, subtraction, and multiplication, conforming to the IEEE‑754 single precision (32‑bit) standard. To speed up multiplication, the design uses Booth’s radix‑4 multiplication algorithm, which reduces partial products and improves throughput with lower hardware overhead. The unit is integrated as a dedicated math coprocessor to accelerate floating‑point computations, which are essential for applications requiring high numerical accuracy and dynamic range, such as digital signal processing, scientific simulations, and real‑time data analysis. Floating‑point representation enables handling of very large or very small values with precision that fixed‑point or integer units cannot achieve, making it suitable for iterative and computationally intensive tasks. The design is modelled using Verilog Hardware Description Language (HDL) and implemented on an Intel Altera FPGA platform. Synthesis results demonstrate efficient resource utilization and high throughput, validating the FPU’s capability to deliver fast and accurate arithmetic processing for embedded systems.

This work presented the design and FPGA implementation of an IEEE-754 compliant 32-bit single precision floating-point arithmetic unit. The proposed system supports floating-point addition, subtraction, and multiplication, with multiplication optimized using Booth’s Radix-4 algorithm to reduce partial products and improve computational efficiency. The complete architecture was modeled using Verilog HDL, verified through functional simulation in the Xilinx Vivado environment, and successfully implemented on the Basys-3 FPGA board. The results demonstrate that the proposed design achieves accurate floating-point computation while maintaining efficient hardware utilization and practical feasibility under FPGA input/output constraints. The use of Booth’s Radix-4 multiplication contributes to reduced computation delay and improved performance compared to conventional multiplication techniques. Overall, the implemented floating-point arithmetic unit provides a reliable and efficient solution suitable for embedded and real-time digital applications.

1.Dr. Ravindra P. Rajput Srujana B Malkapur “Design of Generic Floating Point Pipeline Based Arithmetic Operation for DSP Processor” IEEE Xplore, 978-1-7281-5374- 2/20/$31.00 ©2020 IEEE, pg.no 1059-1064. 2.Manisha Sangwan, An Anita Angeline, Design and Implementation of Single Precision Pipelined Floating Point Co-Processor, 2013 International Conference on Advanced Electronic Systems (ICAES). 3.Ushasree G, R Dhanabal, Dr Sarat Kumar Sahoo, VLSI Implementation of a High Speed Single Precision Floating Point Unit using Verilog, proceedings of 2013 IEEE Conference on Information and Communication Technologies(ICT 2013). 4.F. Mhaboobkhan, K. Kokila, R. Jothikha, and K. L. Preethikha, “ Design of Pipelined Parity Preserving Double Precision Reversible Floating Point Multiplier Using 90 nm Technology,” 2020 6th Int. Conf. Adv. Comput. Commun. Syst. ICACCS 2020, no. 2, pp. 739- 744,2020,doi:10.1109/ICACCS48705.2020.9074209. 5.A. Yadav and I. Chaudhary, “Design of 32 -bit Floating Point Unit for Advanced processors,” Int. J. Eng. Res. Appl., vol. 07, no. 06, pp. 39–46, 2017, doi: 10.9790/9622 0706053946. 6.Shanthala. N1, Nayana. M, Chandrashekar.C, Dr. Siva Yella-MP-al-li “Basic operation performed on Arithmetic Logic Unit (ALU) For 32-Bit Floating Point Numbers”, International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 12 (2017) pp. 3248-3252 Research India Publications. 7.Naresh Grover, M, K Sony, “Design of FPGA based 32-bit Floating Point Arithmetic Unit And verification of its VHDL code using MATLAB”, I.J Information Engineering and Electronics Business, 2014, 1, 1-14 published Online February in MECS. 8.H.H. Saleh, ―H.Fused Floating-Point Arithmetic for DSP, ‖ PhD dissertation, Univ. of Texas, 2008. 9.Swathi.A, G.Srinivasulu “ASIC implementation of a High speed double Precision (64) floating point unit using Verilog”, International journal and magazine of engineering, technology, management and research ISSN 2348-4845. 10.Prashanth B, P.Anil Kumari, G Sreenivasulu,” Design & Implementation of Floating point ALU on a FPGA Processor”, 2012 International Conference on Computing on Computing, Electronics and Electrical Technologies[ICCEET].

© 2025 International Journal of Engineering and Techniques (IJET).

Digital Object Identifier (DOI)

IJET assigns a unique DOI to every accepted article via Zenodo for persistent linking and citation. Your article’s DOI: https://doi.org/{{doi}}

Open DOI About Zenodo DOI

Close