Automatic verification techniques have become important in modern VLSI functional verification due to increasing digital circuit complexity and the effort required for manual UVM testbench development. This paper presents an Enhanced Automatic UVM Testbench Generator (AUTG) using Python-based RTL parsing and System Verilog UVM methodology for efficient RTL design verification. The proposed framework automatically extracts DUT information from RTL files and generates reusable UVM components such as interface, driver, monitor, scoreboard, and testbench modules. Assertion-based verification and functional coverage techniques are implemented to improve bug detection capability and verification completeness. Full Adder, D Flip-Flop (DFF), and FIFO designs are verified using the generated UVM environment. Simulation results and waveform analysis confirm successful verification and correct DUT functionality. The proposed methodology reduces manual coding effort, improves verification productivity, and provides a reusable and scalable verification solution for different RTL designs. The framework also minimizes human errors and supports faster development of UVM-based verification environments for modern VLSI systems.

This paper presented an Enhanced Automatic UVM Testbench Generator (AUTG) developed using Python automation and SystemVerilog UVM methodology for efficient RTL verification. The proposed framework automatically parses RTL design files, extracts DUT information, and generates reusable UVM verification components such as interface, sequence item, driver, monitor, and scoreboard modules. This automation significantly reduces manual coding effort and simplifies the development of verification environments. The proposed framework was successfully validated using Full Adder, D Flip-Flop (DFF), and FIFO designs representing combinational, sequential, and memory-based circuits. Simulation results, waveform analysis, assertion-based verification, and functional coverage confirmed correct DUT functionality and successful verification of all tested designs. The framework achieved 100% functional coverage and generated PASS results for all DUTs. The automatic generation of verification files improved verification productivity, reduced development time, and minimized the possibility of human errors. The generated UVM environment demonstrated reusability and scalability across different RTL designs without requiring significant modifications. Furthermore, the integration of assertions and functional coverage enhanced verification reliability and completeness. Overall, the proposed AUTG framework provides an efficient, reliable, and automated solution for modern VLSI functional verification. The successful verification results demonstrate its effectiveness in reducing verification complexity while improving verification quality, making it a practical approach for future RTL verification applications.

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