
A Comprehensive Survey of Secure and Reconfigurable SoC Architectures for UAV Flight Control Applications | IJET – Volume 12 Issue 1 | IJET-V12I1P66

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ToggleInternational Journal of Engineering and Techniques (IJET)
Open Access • Peer Reviewed • High Citation & Impact Factor • ISSN: 2395-1303
Volume 12}, Issue 1 | Published: February 2026
Author:Kalakurasa Rakesh, Moturi Satyanarayana
DOI: https://doi.org/{{doi}} • PDF: Download
Abstract
Unmanned Aerial Vehicles (UAVs) are increasingly deployed in safety- and mission-critical applications, making them attractive targets for cyber, physical, and hardware-based attacks. Traditional UAV controllers rely on static embedded architectures that lack runtime adaptability and robust hardware- level security. This survey investigates secure System-on-Chip (SoC) architectures for UAV control, with a focus on FPGA- SoC platforms and Dynamic Partial Reconfiguration (DPR). The proposed DRS-UAV-SoC architecture has been developed as a way to create a secure, dynamic, and adaptable UAV control system. DRS-UAV-SoC architecture combines both static flight control logic with dynamic reconfigured security modules and thus provides multi-layered security via adaptive means, while not interrupting or disrupting real-time control loops. Based on performance and security analyses conducted, it has been proven that dynamic reconfiguration of security modules is feasible. There are clear advantages of using dynamic reconfiguration and security modules for building resilient UAV control systems.
This paper presents a comprehensive survey of secure and reconfigurable SoC architectures for UAV flight control applications. The survey systematically reviews UAV avionics architectures, security threats specific to flight control systems, hardware security mechanisms in SoCs, and the role of reconfigurable computing, including dynamic partial reconfiguration, in enhancing system resilience. Existing approaches are analysed and classified based on architectural design, security features, reconfiguration support, and UAV applicability. A critical assessment reveals key limitations in current research, such as static security assumptions, limited exploitation of runtime reconfiguration for security, and the absence of control-aware security analysis. Finally, open research challenges and future directions are discussed, emphasizing the need for control–security co-design and dynamic reconfigurable SoC frameworks tailored to safety-critical UAV applications.
Keywords
Unmanned Aerial Vehicles, Flight Control Systems, System-on-Chip, FPGA-SoC, Hardware Security, Dynamic Reconfiguration
Conclusion
This survey and research study systematically investigates secure The study will focus on Unmanned Aerial Vehicle (UAV) System On Chip (SoC) architectures that have an emphasis on dynamic reconfigurability and hardware-based security. The analysis starts with an examination of the various types of UAV threats and categorizes the various types of UAV attacks. From there the study examines the limitations of using typical micro-controller (MCU) based flight controllers and static Field Programmable Gate Array (FPGA) SoC designs, both of which lack the ability to implement runtime security mechanisms in conjunction with the strict real-time control requirement. The Dynamic Reconfigurable Secure UAV SoC (DRS-UAV-SoC) architecture, as defined in this paper, divides the total system architecture into two separate regions: A static region that will be used for all flight critical control functions and a reconfigurable region that can adapt to security threats at runtime by using the Dynamic Partial Reconfiguration feature of an FPGA SoC device. By using Dynamic Partial Reconfiguration in ways that move beyond traditional performance improvement and fault tolerance applications of Dynamic Partial Reconfiguration to include the development of real-time security adaptations and moving target defenses, the proposed architecture creates a new paradigm in the security of cyber-physical systems used in UAVs. Experimental results demonstrate that reconfiguration latencies in the range of 5 to 25 milliseconds and moderate FPGA resource utilization will work well on small to medium size UAV platforms and support the concept of integrating this technology into UAVs in operational settings. Overall, the DRS-UAV-SoC architecture establishes a framework that unifies considerations of real-time control, hardware security and dynamic reconfiguration in order to provide a foundation upon which resilient and secure, next generation autonomous UAV systems can be developed for safety-critical civilian and defense applications.
References
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Cite this article
APA
Kalakurasa Rakesh, Moturi Satyanarayana (February 2026). A Comprehensive Survey of Secure and Reconfigurable SoC Architectures for UAV Flight Control Applications. International Journal of Engineering and Techniques (IJET), 12(1). https://doi.org/{{doi}}
Kalakurasa Rakesh, Moturi Satyanarayana, “A Comprehensive Survey of Secure and Reconfigurable SoC Architectures for UAV Flight Control Applications,” International Journal of Engineering and Techniques (IJET), vol. 12, no. 1, February 2026, doi: {{doi}}.
