This article includes an experimental investigation of the effect of floorplan utilization on routing congestion and physical implementation feasibility in the PicoRV32 RISC-V processor using the SKY130 Process Design Kit and the OpenLane open-source ASIC flow. Several RTL-to-GDSII implementation runs with floorplan usage values ranging from 50% to 70% were conducted under controlled implementation scenarios. The effects of usage scaling on core area, placement density, routing behavior, congestion increase, and implementation efficacy were thoroughly examined. The results of the trials demonstrate that excessive consumption significantly increases routing congestion and diminishes routability, whereas greater usage decreases core dimensions and enhances area efficiency. Although satisfactory implementation closure was achieved up to 60% utilization, higher use values caused significant routing congestion issues during global routing. Furthermore, implementation behavior at various placement densities was evaluated using power analysis. The study provides real usage restrictions and congestion-aware physical design insights for open-source ASIC implementation methods.

The impacts of floorplan use on routing congestion and implementation viability in the PicoRV32 RISC-V processor employing OpenLane and SKY130 technologies were investigated experimentally in this study. Several RTL-to-GDSII implementation studies were carried out with utilization circumstances ranging from 50% to 70%. However, during physical installation, vigorous consumption greatly increased placement density and routing congestion. Reduced availability of routing resources and high congestion overflow caused routing feasibility to rapidly deteriorate beyond 60% utilization. Up to 60% utilization led to successful RTL-to-GDSII implementation closure; greater utilization circumstances resulted in routing instability and implementation failure. As a result, the study demonstrates how crucial congestion-aware optimization is when implementing physical designs. The experimental findings verify that rather than depending exclusively on aggressive area reduction goals, physical design optimization must balance area efficiency, routing feasibility, and implementation stability. The study that is being presented sets realistic use limits for the installation of congestion-aware open-source ASICs utilizing SKY130 technology.

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