Machine learning-based prediction techniques have emerged as an effective solution for early estimation of VLSI design parameters, reducing the need for repeated synthesis and simulation operations. This work presents a machine learning-based framework for predicting power consumption, silicon area, and propagation delay using synthesis-oriented hardware datasets. The proposed approach employs Linear Regression, Decision Tree, Random Forest, and a combined DT+RF model using hardware-related input features including bit width, gate count, and flip-flop count. The models are trained on a dataset generated from Cadence Genus synthesis of both combinational and sequential digital circuits. Validation was performed using 8-bit, 16-bit, and 32-bit Arithmetic Logic Units (ALUs) and Up-Down Counters synthesised on the TSMC 180 nm technology library. Comparative analysis demonstrates that Decision Tree achieved the highest prediction accuracy, while Random Forest provided superior generalisation capability. The combined DT+RF model offered a balanced trade-off between accuracy and robustness. The proposed framework enables rapid early-stage VLSI parameter estimation and significantly reduces design exploration time.

A machine learning-based framework for predicting key VLSI design parameters, including power consumption, silicon area, and propagation delay, was presented in this work. Synthesis-oriented datasets containing hardware-related features such as bit width, gate count, and flip-flop count were used to train and evaluate Linear Regression, Decision Tree, Random Forest, and a combined DT+RF model. Validation was performed using Cadence Genus synthesis reports of ALU and Up-Down Counter circuits with 8-bit, 16-bit, and 32-bit architectures. Comparative analysis demonstrated that Decision Tree achieved the highest prediction accuracy and produced results that were closest to the Cadence synthesis values. Random Forest exhibited strong prediction performance and superior generalisation capability for unseen circuit configurations, while the combined DT+RF model provided a balanced trade-off between prediction accuracy and robustness. Linear Regression showed comparatively larger prediction errors due to its limited ability to model nonlinear relationships present in synthesis-oriented VLSI datasets. The proposed framework significantly reduces dependence on repeated synthesis iterations and enables rapid early-stage estimation of power, area, and delay parameters. Future work may focus on extending the framework to larger industrial datasets, advanced technology nodes, and deep learning-based optimisation techniques. Additional VLSI parameters such as routing congestion, leakage power, thermal behaviour, and resource utilisation can also be incorporated to further enhance prediction capability.

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