Growing reliance on battery-powered embedded and IoT platforms has made power-aware processor design a fundamental engineering concern rather than merely a desirable attribute. This work details the design and physical realization of a 64-bit scalar RISC processor architecture aimed at simultaneously maximizing instruction throughput and minimizing on-chip power overhead. Instruction execution is organized across five synchronous pipeline stages—Fetch, Decode, Execute, Memory access, and Write-Back—so that each stage operates independently on successive instructions without stalling the overall flow. The central challenge of reducing unnecessary switching activity across the wide 64-bit data buses is tackled through the deliberate placement of Integrated Clock Gating (ICG) cells within the clock distribution tree. When the instruction decoder determines that a functional unit—such as the 64-bit Barrel Shifter Rotator or the 64-operation ALU—is not required for the current instruction, the corresponding ICG cell isolates that unit from the clock, suppressing wasteful internal node transitions. The entire design was captured in Verilog HDL and taken through ASIC synthesis on the Cadence Genus platform targeting the GPDK 90nm CMOS technology node. Post-synthesis analysis confirms clean timing closure at 100 MHz with a compact gate count, and comparative evaluation shows the resulting silicon footprint to be substantially smaller than that of vector-oriented processor designs occupying the same application space.

This paper has presented the end-to-end design, synthesis, and physical verification of a 64-bit scalar RISC processor developed for embedded applications where area and power budgets are tightly constrained. The five-stage pipeline organization provides the throughput necessary for real-time workloads, while the strategic insertion of ICG cells across the clock distribution network prevents idle execution units from consuming dynamic power between active instruction cycles. Post-synthesis results at 100 MHz confirm zero worst-negative-slack, a total instance count of 233,051, and on-chip power consumption of approximately 3.21 mW—metrics that collectively demonstrate the viability of the scalar pipelined approach for IoT and battery-operated embedded platforms. Compared with vector processor architectures of equivalent word width, the proposed design offers a substantially more compact footprint and avoids the scheduling overheads associated with SIMD lane management, making it well suited to general-purpose embedded computation where silicon efficiency must be prioritized alongside performance.

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