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Paper Title : A Pipelined ADC With Sub-ADC Based on Flash–Ramp Architecture

ISSN : 2395-1303
Year of Publication : 2020
10.29126/23951303/IJET-V6I2P9

Authors: -Himanshu Shekhar, Dr Bharti Chourasia

         


Abstract
This work is base on the pipeline ADCs architecture. Pipeline ADCs are convenient alternatives to time interleaving. As the stage of the pipeline is simpler asd compare to a full converter, the design area and power are competitive. The pipeline ADC design with two or more stages in which every stage is of a low resolution ADC, and combining these stages results in a higher resolution.The design ADC consists of channels for high operating speed and every channel consist of a pipelined flash and ramp analog 5to digital converter architecture with reduce power and a optimize area. The sample ADC design in a 50-nanometer CMOS technology with 8-bit of resolution. The supply voltage is 1.2V

Reference
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Keywords
Flash ADC, Ramp ADC, Pipelined, SAR, Dual Slop